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preliminary w24l11 128k 8 cmos static ram publication release date: october 1999 - 1 - revision a1 general description the w24l11 is a normal-speed, very low-power cmos static ram organized as 131072 8 bits that operates on a wide voltage range from 3.0v to 3.6v power supply. this device is manufactured using winbond's high performance cmos technology. features ? low power consumption: ? active: 144 mw (max.) ? access time: 70 ns ? single 3.3v power supply ? fully static operation ? all inputs and outputs directly ttl compatible ? three-state outputs ? battery back-up operation capability ? data retention voltage: 2v (min.) ? packaged in 600 mil dip, 450 mil sop, standard type one, tsop (8 mm 20 mm) , small type one and tsop (8 mm 13.4 mm) pin configurations block diagram v a8 a9 we 1 2 3 4 5 24 25 26 27 28 nc a7 a6 a5 a12 a4 a3 a2 a1 6 7 8 9 20 21 22 23 a11 oe a1 0 cs1 i/o 8 i/o 7 i/o 6 i/o 5 10 11 12 13 16 17 18 19 a0 i/ o 2 i/ o 3 i/ o 1 14 15 i/o 4 a13 v a14 a16 32 31 30 29 a15 cs2 dd ss 1 32-pin 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 i/o8 a15 a12 a7 a6 a5 a4 v cs2 we a13 a8 dd a11 a9 nc a14 a16 v ss we oe precharge ckt. a13 a1 a0 a10 cs1 a16 a14 a4 a3 a7 a6 a9 i/o1 : pin description symbol description a0 ? a16 address inputs i/o1 ? i/o8 data inputs/outputs cs1 , cs2 chip select input we write enable input oe output enable input v dd power supply v ss ground nc no connection
preliminary w24l11 - 2 - truth table cs1 cs2 oe we mode i/o1 ? i/o8 v dd current h x x x not selected high z i sb , i sb1 x l x x not selected high z i sb , i sb1 l h h h output disable high z i dd l h l h read data out i dd l h x l write d ata in i dd dc characteristics absolute maximum ratings parameter rating unit supply voltage to v ss potential -0.5 to +4.6 v input/output to v ss potential -0.5 to v dd +0.5 v allowable power dissipation 1.0 w storage temperature -65 to +150 c operating temperature 0 to 70 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability o f the device. operating characteristics (v dd = 3.0v to 3.6v; v ss = 0v; t a ( c) = 0 to 70) parameter sym. test conditions min. max. unit input low voltage v il - -0.5 +0.6 v input high voltage v ih - +2.0 v dd +0.5 v input leakage current i li v in = v ss to v dd -1 +1 a output leakage current i lo vi/o = v ss to v dd , cs1 = v ih (min.) or cs2 = v il (max.) or oe = v ih (min.) or we = v il (max.) -1 +1 a output low voltage v ol i ol = +2.1 ma - 0.4 v output high voltage v oh i oh = -1.0 ma 2.2 - v operating power supply current i dd cs1 = v il (max.) and cs2 = v ih (min.), i/o = 0 ma, cycle = min. duty = 100% - 40 ma
preliminary w24l11 publication release date: october 1999 - 3 - revision a1 operating characteristics, continued parameter sym. test conditions min. max. unit standby power supply current i sb cs1 = v ih (min.) or cs2 = v il (max.) cycle = min. duty = 100% - 1 ma i sb1 cs1 v dd -0.2v or ll - 50 a cs2 0.2v l - 100 note: typical parameter is measured under ambient temperature t a = 25 c and v dd = 3.3v capacitance (v dd = 3.3 v, t a = 25 c, f = 1 mhz) parameter sym. conditions max. unit input capacitance c in v in = 0v 6 pf input/output capacitance c i/o v out = 0v 8 pf note: these parameters are sampled but not 100% tested. ac characteristics ac test conditions parameter conditions input pulse levels 0v to 3.0v input rise and fall times 5 ns input and output timing reference level 1.5v output load see the drawing below ac test loads and waveform 90% 90% 5 ns 10% 5 ns 10% output output 3.0 v 0 v 100 pf including jig and scope 5 pf including jig and scope 1 ttl 1 ttl clz, olz, chz, ohz, whz, ow (for t t t t t t )
preliminary w24l11 - 4 - ac characteristics, continued (v dd = 3.0v to 3.6 v; v ss = 0v; t a ( c) = 0 to 70) read cycle parameter symbol w24l11-70l/ll unit min. max. read cycle time t rc 70 - ns address access time t aa - 70 ns chip select access time t acs - 70 ns output enable to output valid t aoe - 35 ns chip selection to output in low z t clz * 10 - ns output enable to output in low z t olz * 5 - ns chip deselection to output in high z t chz * - 30 ns output disable to output in high z t ohz * - 30 ns output hold from address change t oh 10 - ns ? these parameters are sampled but not 100% tested write cycle parameter symbol w24l11-70l/ll unit min. max. write cycle time t wc 70 - ns chip selection to end of write t cw 55 - ns address valid to end of write t aw 55 - ns address setup time t as 0 - ns write pulse width t wp 50 - ns write recovery time cs1 , cs2, we t wr 0 - ns data valid to end of write t dw 45 - ns data hold from end of write t dh 0 - ns write to output in high z t whz * - 25 ns output disable to output in high z t ohz * - 25 ns output active from end of write t ow 5 - ns ? these parameters are sampled but not 100% tested
preliminary w24l11 publication release date: october 1999 - 5 - revision a1 timing waveforms read cycle 1 (address controlled) address t rc t aa t oh t oh d out read cycle 2 (chip select controlled) d out cs1 t clz t acs chz t cs2 read cycle 3 (output enable controlled) address t rc cs1 t aa oe t aoe t olz t oh t acs d out clz t chz t t ohz cs2
preliminary w24l11 - 6 - timing waveforms, continued write cycle 1 address oe t wc t wr we d out d in t wp t as t ohz (1, 4) t dw t dh t aw cs1 t cw cs2 write cycle 2 ( oe = v il fixed) we d out d in t as t dh t wp t whz dw t (2) (3) t ow t oh aw t (1, 4) t cw t wr address t wc cs1 cs2 notes: 1. during this period, i/o pins are in the output state, so input signals of opposite phase to the outputs should not be applie d. 2. the data output from d out are the same as the data written to d in during the write cycle. 3. d out provides the read data for the next address. 4. transition is measured 500 mv from steady state with c l = 5 pf. this parameter is guaranteed but not 100% tested.
preliminary w24l11 publication release date: october 1999 - 7 - revision a1 data retention characteristics (t a ( c) = 0 to 70) parameter sym. test conditions min. typ. max. unit v dd for data retention v dr cs1 v dd -0.2v or cs2 0.2v 2.0 - - v data retention current i dddr cs1 v dd -0.2v or cs2 0.2v, v dd = 3v - - 50 a chip deselect to data retention time t cdr see data retention waveform 0 - - ns operation recovery time t r t rc * - - ns * read cycle time data retention waveform t cdr - 0.2v dd v v dd cs1 t r cs1 v dr 2v = > = > 0.9 dd v 0.9 dd v cs2 0v cs2 0.2v < = < =
preliminary w24l11 - 8 - ordering information part no. access time (ns) operating voltage (v ) operating temperature ( c ) standby current max.( a) package w24l11-70ll 70 3.0v to 3.6v 0 to 70 50 600 mil dip w24l11s-70ll 70 3.0v to 3.6v 0 to 70 50 450 mil sop w24l11t-70ll 70 3.0v to 3.6v 0 to 70 50 standard type one tsop w24l11q-70ll 70 3.0v to 3.6v 0 to 70 50 small type one tsop w24l11- 70l 70 3.0v to 3.6v 0 to 70 100 600 mil dip w24l11s-70l 70 3.0v to 3.6v 0 to 70 100 450 mil sop w24l11t-70l 70 3.0v to 3.6v 0 to 70 100 standard t ype one tsop w24l11q-70l 70 3.0v to 3.6v 0 to 70 100 small type one tsop notes: 1. winbond reserves the right to make changes to its products without prior notice. 2. purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
preliminary w24l11 publication release date: october 1999 - 9 - revision a1 package dimensions 32-pin p-dip 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimensions d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. 1.37 1.22 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.33 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.41 0.25 3.94 0.46 4.06 0.56 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.20 3.05 0.25 3.30 0.36 3.56 0.555 0.550 0.545 14.10 13.97 13.84 17.02 15.24 14.99 15.49 0.600 0.590 0.610 2.29 2.54 2.79 0.090 0.100 0.110 b 1 1 e e 1 a 1.650 1.660 41.91 42.16 015 0.085 2.16 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches 15 0 seating plane e a 2 a a c e base plane 1 a 1 e l a s 1 e d 1 b b 32 1 16 17 32-pin sop wide body 1 17 32 16 y e d s seating plane b a a eh l l e e 1 c e 1 1 e a 2 see detail f detail f 1. dimensions d max. & s include mold flash or tie bar burrs. 2. dimension b does not include dambar protrusion/intrusion. 3. dimensions d & e include mold mismatch and determined at the mold parting line. . notes: 4. controlling dimension: inches 5. general appearance spec should be based on final visual inspection spec. 0.20 0.15 0.008 0.006 symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a l e 1 2 e 0.012 0.31 0.118 3.00 0.004 0.101 0.014 0.106 0.016 0.111 0.020 2.57 0.36 0.10 2.69 0.41 2.82 0.51 0.047 0.004 0 10 0.805 0.055 0.817 0.063 1.19 20.45 1.40 20.75 1.60 0.556 0.556 0.546 14.38 14.12 13.87 10 0 0.10 11.43 11.30 11.18 0.450 0.445 0.440 0.58 0.79 0.99 0.023 0.031 0.039 1.12 1.27 1.42 0.044 0.050 0.056 s 0.91 0.036
preliminary w24l11 - 10 - package dimensions, continued 32-pin standard type one tsop a a a 2 1 l l 1 y c e h d d b e m 0.10(0.004) min. nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d controlling dimension: millimeters dimension in inches 0.047 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.005 0.006 0.007 0.720 0.724 0.728 0.311 0.315 0.319 0.780 0.787 0.795 0.020 0.016 0.020 0.024 0.031 0.000 0.004 1 35 0.002 1.20 0.05 0.15 1.05 1.00 0.95 0.17 0.12 18.30 7.90 19.80 0.40 0.00 1 0.20 0.23 0.15 0.17 18.40 18.50 8.00 8.10 20.00 20.20 0.50 0.50 0.60 0.80 0.10 35 dimension in mm __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ __ 1 32-pin small type one tsop a a a 2 1 l l 1 y c e h d d b e 1 controlling dimension: millimeters min. dimension in mm nom. max. min. nom. max. symbol a a b c d e e l l y 1 1 2 a h d 11.70 13.20 0.675 1.25 0.05 0.15 1.05 1.00 0.95 0.17 0.14 0.30 0.00 0.20 0.27 0.15 0.16 11.80 11.90 13.40 13.60 0.50 0.50 0.70 0.10 0.049 0.006 0.041 0.039 0.037 0.007 0.008 0.009 0.00560.0059 0.0062 0.461 0.465 0.469 7.90 8.00 8.10 0.311 0.315 0.319 0.520 0.528 0.536 0.020 0.012 0.020 0.028 0.027 0.000 0.004 0.002 035 035 dimension in inches
preliminary w24l11 publication release date: october 1999 - 11 - revision a1 version history version date page description a1 oct. 1999 - initial issued headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5796096 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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